1. Field of the Invention
The present invention relates to voltage down converters used in semiconductor memory devices.
2. Description of the Background Art
To accommodate increased storage capacity in the semiconductor memory devices, a great effort has been made to achieve higher densification and higher integration. One technique that realizes the higher densification and higher integration is a miniaturization of component elements.
The advancement in miniaturization of component elements has an adverse effect of decrease in breakdown voltage of insulated gate field effect transistors (hereinafter referred to as MOS transistors), which are component elements. Therefore, when a power supply voltage received from an external source as an operating power supply voltage is directly supplied to an MOS transistor, the power supply voltage exceeds the breakdown voltage of the MOS transistor, and a sufficient reliability cannot be secured with regard to factors such as breakdown voltage of insulated films.
Hence, in dynamic semiconductor memory devices hereinafter referred to as DRAM) with the storage capacity equal to or exceeding 16 Mbit, for example, an external power supply voltage is lowered to the level of an internal power supply voltage and each component element is operated with the internal power supply voltage to secure a sufficient reliability of each component element.
FIG. 7 is a schematic block diagram showing an overall structure of an DRAM 140 as an example of a conventional semiconductor memory device. In FIG. 7, DRAM 140 includes an internal circuit 90, a voltage down converter 91 and a circuit 92 operated with an external power supply voltage.
Voltage down converter 91 lowers the level of an external power supply voltage VCC supplied to a VCC power supply node to generate an internal power supply voltage VCCS on a VSS power supply node.
Internal circuit 90 operates using internal power supply voltage VCCS on a VCCS power supply node as an operating power supply. Such internal circuit 90 includes a memory cell array having a plurality of MOS transistors as component elements, a sense amplifier performing a sense amplification of data read out from the memory cell array and so on.
Circuit 92 operated with an external power supply voltage operates with external power supply voltage VCC on VCC power supply node as an operating power supply. Such circuit 92 operated with external power supply voltage includes a circuit performing data input/output.
Here, internal circuit 90, voltage down converter 91 and circuit 92 operated with an external power supply voltage receive a power supply voltage VSS (hereinafter referred to as a ground voltage) of a different level from external power supply voltage VCC at the VSS power supply node.
Therefore, in the memory cell or the sense amplifier, that is, internal circuit 90, MOS transistors, which are their component elements, receive internal power supply voltage VCCS generated by lowering external power supply voltage VCC as an operating power supply voltage.
Thus, even when the higher densification and higher integration of the memory cell array is achieved and the breakdown voltage of the MOS transistor, which is a component element, decreases as a result of miniaturization, a voltage applied to a gate insulated film thereof can be suppressed to a low level. Therefore, the reliability of the component elements can be secured and a stable and reliable operation of DRAM 140 as a whole can be obtained.
FIG. 8 is a circuit diagram showing a structure of conventional voltage down converter 91 shown in FIG. 7. In FIG. 8, voltage down converter 91 includes an operational amplifier 70 and a P channel MOS transistor 77.
Operational amplifier 70 receives an internal power supply voltage VCCS, which is to be an output of voltage down converter 91, at its positive, input and receives a reference voltage VREF from a reference voltage generation circuit not shown at its negative input. Operational amplifier 70 performs an operational amplification on reference voltage VREF and an internal power supply voltage VDD to output a control voltage VOUT at an output node 75.
Then, P channel MOS transistor 77, under the control of control voltage VOUT, supplies a current from the VCC power supply node to a power supply node 78 to adjust a voltage level of internal power supply voltage VCCS at power supply node 78.
Operational amplifier 70 forms a current mirror type operational amplifier including P channel MOS transistors 71 and 72, N channel MOS transistors 73 and 74 and constant-current source circuit 76 as shown in FIG. 8.
Here, P channel MOS transistor 71 and N channel MOS transistor 73, and P channel MOS transistor 72 and N channel MOS transistor 74 are connected in parallel with each other and both pairs are connected between VCC power supply node and one terminal of constant-current source circuit 76.
Further, N channel MOS transistor 73 receives reference voltage VREF at its gate, whereas N channel MOS transistor 74 receives internal power supply voltage VCCS on power supply node 78 at its gate.
Constant-current source circuit 76 has another terminal connected to the VSS power supply node. Constant-current source circuit 76 also controls the amount of current of operational amplifier 70 such that a sum of a current amount flowing from N channel MOS transistor 73 and a current amount flowing from N channel MOS transistor 74 is always at a constant level.
Control voltage VOUT of operational amplifier 70 is output from output node 75, which is a connection point of P channel MOS transistor 71 and N channel MOS transistor 73.
A connection node 79, that is a connection point of P channel MOS transistor 72 and N channel MOS transistor 74 is connected to respective gates of P channel MOS transistor 71 and P channel MOS transistor 72.
Operational amplifier 70 operates with external power supply voltage VCC and ground voltage VSS as operating power supply, and when a level of internal power supply voltage VCCS rises above a level of reference voltage VREF, operational amplifier 70 raises a voltage level of output node 75, that is control voltage VOUT, up to a level of external power supply voltage VCC at the highest.
As a result, the channel resistance of P channel MOS transistor 77 receiving control voltage VOUT at its gate increases to reduce the current supply from the VCC power supply node to power supply node 78 and to lower the voltage level of internal power supply voltage VCCS.
On the other hand, when internal power supply voltage VCCS falls below the level of reference voltage VREF, operational amplifier 70 lowers control voltage VOUT to the level of ground voltage VSS (=0 V) at the lowest.
As a result, P channel MOS transistor 77 becomes conductive and amount of current supplied from the VCC power supply node to power supply node 78 increases and the level of internal power supply voltage VCCS is raised.
Thus, voltage down converter 91 feeds back internal power supply voltage VCCS and compares internal power supply voltage VCCS with reference voltage VREF. Then, the result of comparison is amplified to generate control voltage VOUT, which is used for controlling P channel MOS transistor 77 used for driving the power supply. Thus, voltage down converter 91 operates to hold internal power supply voltage VCCS at a constant voltage level, that is the level of reference voltage.
In voltage down converter 91 shown in FIG. 8. however, in some cases the voltage level of internal power supply voltage VCCS stays at a level significantly lower than the level of reference voltage VREF, depending on an operation state of internal circuit 90 which uses internal power supply voltage VCCS output from voltage down converter 91 as an operating power supply, and the voltage level of internal power supply voltage VCCS cannot be secured at a target value, which is the voltage level of reference voltage VREF.
Assume that internal circuit 90 operates and consumes a current on power supply node 78. As described above, voltage down converter 91 shown in FIG. 8 is responsive to the change in the voltage level on power supply node 78 and, when internal power supply voltage VCCS falls below the level of reference voltage VREF, lowers control voltage VOUT to render P channel MOS transistor 77 used for driving the power supply conductive. FIG. 9 is a timing chart of control voltage VOUT and internal power supply voltage VCCS in conventional voltage down converter 91. The ordinate represents a voltage V and the abscissa represents a time.
The period from time t1 to time t2 represents an operating period of internal circuit 90. Here, assume that the amount of current consumption of internal circuit 90 from power supply node 78 is high. In this case, in response to the fall of internal power supply voltage VCCS from time t1, the voltage level of control voltage VOUT falls to increase the supply of current from P channel MOS transistor 77 to power supply node 78.
Operational amplifier 70 generates control voltage VOUT by comparing internal power supply voltage VCCS and reference voltage VREF and amplifying the result of comparison. Hence, a certain time is necessary for compensating the fall of internal power supply voltage VCCS and recovering internal power supply voltage VCCS to the level of reference voltage VREF. As a result, during the time period from time t1 to time t2, which is the operating period of internal circuit 90, internal power supply voltage VCCS becomes significantly lower than reference voltage VREF.
In addition, P channel MOS transistor 77 used for driving the power supply is driven based on control voltage VOUT which is controlled in an analog manner in the range between the level of ground voltage VSS and the level of external power supply voltage VCC. Therefore, to make a current flowing from the VCC power supply node to power supply node 78 variable according to the variation in potential of control voltage VOUT, P channel MOS transistor 77 must have a wider channel width.
One way to solve the problem of requirement of the P channel MOS transistor with wide channel width is to provide a voltage down converter 910 shown in FIG. 10. Voltage down converter 910 is formed by adding a buffer 82 and a P channel MOS transistor 83 to voltage down converter 91 and replacing P channel MOS transistor 77 with a P channel MOS transistor 84. Buffer 82 is constituted of two inverters connected in series. P channel MOS transistor 84 has a narrower channel width than that of P channel MOS transistor 77. Buffer 82 receives control voltage VOUT on node 75 as an input, converts control voltage VOUT, which is an analog signal, to a digital signal of an H (logical high) level or an L (logical low) level and supplies the resulting digital signal to the gate of P channel MOS transistor 83. Thus, P channel MOS transistor 83 is inactivated when an H level signal is supplied from buffer 82 and is activated when an L level signal is supplied from buffer 82. P channel MOS transistor 84 operates in the same manner as P channel MOS transistor 77 of voltage down converter 91 based on analog control voltage VOUT.
Thus, P channel MOS transistor 83 is activated/inactivated in a digital manner through control voltage VOUT, and P channel MOS transistor 84 is activated/inactivated in an analog manner through control voltage VOUT. As a current is supplied from the VCC power supply node to power supply node 78 via two P channel MOS transistors 83 and 84, the level of the voltage on power supply node 78 can be maintained at the level of internal power supply voltage VCCS through P channel MOS transistors 83 and 84 with a narrow channel width even when control voltage VOUT varies in an analog manner.
In voltage down converter 910, however, when external power supply voltage VCC varies, the driveability of P channel MOS transistor 84 per channel width varies. Here, the channel width of P channel MOS transistor 84 is constant regardless of the level of external power supply voltage VCC. Therefore, assume that the channel width of P channel MOS transistor 84 is determined such that internal power supply voltage VCCS is in the predetermined range even when the level of external power supply voltage VCC is at an upper limit of the standard. If the level of external power supply voltage VCC changes to a lower limit of the standard, the driveability of P channel MOS transistor 84 becomes insufficient to maintain the level of internal power supply voltage VCCS in the predetermined range.
In addition, similarly to voltage down converter 91, during the operating period of internal circuit 90, internal power supply voltage VCCS becomes significantly lower than the level of reference voltage VREF because voltage down converter 910 adapts a structure in which internal power supply voltage VCCS is compared with reference voltage VREF.
Therefore, an object of the present invention is to provide a voltage down converter capable of maintaining the internal power supply voltage at the level of the reference voltage even during a period when the internal circuit of the semiconductor memory device operates and falls the internal power supply voltage by a significant amount from the level of reference voltage.
A voltage down converter according to the present invention is provided with a first voltage down converting circuit to lower an external power supply voltage on a first input node to generate an internal power supply voltage at a first output node, and a second voltage down converting circuit to lower the external power supply voltage on a second input node to generate the internal power supply voltage at a second output node, for operating an internal circuit by the internal power supply voltage generated on the first output node or the second output node, wherein the first voltage down converting circuit includes; a first voltage down converting partial circuit to lower the external power supply voltage by passing an operating current from the first input node to the first output node to generate the internal power supply voltage on the first output node, and a digital driving circuit to drive the first voltage down converting partial circuit to maintain a voltage on the first output node at the internal power supply voltage by varying the operating current of the first voltage down converting partial circuit stepwise according to a level of the external power supply voltage or the internal power supply voltage only during a period when the internal power supply voltage falls below a predetermined voltage, and the second voltage down converting circuit includes a comparison circuit to perform an operational amplification on a result of comparison of the internal power supply voltage on the second output node and an internal reference voltage to output the result of amplification, and a second voltage down converting partial circuit to receive an output of the comparison circuit and to lower the external power supply voltage to generate the internal power supply voltage on the second output node.
In the voltage down converter according to the present invention, the first voltage down converting circuit passes an operating current from the first input node of the first voltage down converting partial circuit to the first output node without comparing the internal power supply voltage with the reference voltage, to lower the external power supply voltage to the level of the internal power supply voltage. The digital driving circuit sets the operating current of the first voltage down converting partial circuit at the reference current value when the external power supply voltage or the internal power supply voltage is at the level of the-reference voltage, and drives the first voltage down converting partial circuit such that the operating current of the first voltage down converting partial circuit is decreased stepwise from the reference current value when the external power supply voltage or the internal power supply voltage rises above the level of the reference voltage, and that the operating current of the first voltage down converting partial circuit is increased stepwise from the reference current value when the external power supply voltage or the internal power supply voltage falls below the level of the reference voltage. Then, the first voltage down converting partial circuit passes such operating current from the first input node to the first output node that the voltage on the first output node is maintained at the level of internal power supply voltage based on the drive from the digital driving circuit.
In addition, the second voltage down converting circuit lowers the external power supply voltage to the internal power supply voltage by comparing the internal power supply voltage with internal reference voltage. The comparison circuit compares the internal power supply voltage with the internal reference voltage and, when the internal power supply voltage is higher than the level of the internal reference voltage, the second voltage down converting partial circuit lowers the external power supply voltage by a large amount to lower the internal power supply voltage and when the internal power supply voltage is lower than the level of the internal reference voltage, the second voltage down converting partial circuit lowers the external power supply voltage by a small amount to raise the internal power supply voltage.
The first voltage down converting circuit and the second voltage down converting circuit are connected in parallel with the internal circuit of the semiconductor memory device. During the period when the internal power supply voltage falls below a level of a predetermined voltage, the internal power supply voltage is supplied to the internal circuit from the first voltage down converting circuit. Other than the period when the internal power supply voltage falls below the predetermined voltage level, the internal power supply voltage is supplied to the internal circuit from the second voltage down converting circuit. Thus, according to the present invention, the voltage down converter can always supply a stable internal power supply voltage even if the internal power supply voltage falls by a significant amount because of the sense amplification of the data read out from the memory cell. In addition, regardless of the variation in the external power supply voltage or the internal power supply voltage, voltage down converter can supply a stable internal power supply voltage to the internal circuit.
Preferably, the first voltage down converting partial circuit of the first voltage down converting circuit is constituted of MOS transistors with variable channel width and the digital driving circuit drives the first voltage down converting partial circuit to change the channel width of the MOS transistor stepwise according to the level of the external power supply voltage or the internal power supply voltage.
The digital driving circuit sets the channel width of the MOS transistor at such channel width that the operating current of the reference current value flows when the external power supply voltage or the internal power supply voltage is at the level of the reference voltage; sets the channel width of the MOS transistor at such channel width that the current generated by decreasing the current stepwise from the reference current value flows when the external power supply voltage or the internal power supply voltage rises above the level of the reference voltage; and sets the channel width of the MOS transistor at such channel width that the current generated by increasing the current amount stepwise from the reference current value flows when the external power supply voltage or the internal power supply voltage falls below the reference voltage. Then, the first voltage down converting partial circuit passes such operating current from the first input node to the first output node that the voltage on the first output node is maintained at the level of the internal power supply voltage based on the drive from the digital driving circuit. Hence, according to the present invention, regardless of the variation of the external power supply voltage or the internal power supply voltage, the voltage on the first output node can be maintained at the level of the internal power supply voltage through the change in the channel width of the MOS transistor.
Preferably, the first voltage down converting partial circuit in the first voltage down converting circuit is constituted of a plurality of MOS transistors having a same channel width and connected in parallel between the first input node and the first output node, and the digital driving circuit drives the first voltage down converting partial circuit to change stepwise the number of MOS transistors to be activated among the plurality of MOS transistors according to the level of the external power supply voltage.
The digital driving circuit sets the number of the MOS transistors to be activated at such number that the operating current of the reference current value flows when the external power supply voltage is at the level of the reference voltage; sets the number of the MOS transistors at such number that the current generated by decreasing the current amount stepwise from the reference current value flows when the external power supply voltage becomes higher than the reference voltage; and sets the number of the MOS transistors at such number that the current generated by increasing the reference current value stepwise flows when the external power supply voltage falls below the reference voltage. Thus, the first voltage down converting partial circuit passes such operating current that the voltage on the first output node is maintained at the level of the internal power supply voltage by changing the number of MOS transistors to be activated based on the drive from the digital driving circuit. Thus, according to the present invention, regardless of the variation in the external power supply voltage, the voltage on the first output node can be maintained at the level of the internal power supply voltage through the change in the number of the MOS transistors to be activated.
Preferably, the first voltage down converting partial circuit in the first voltage down converting circuit is constituted of a plurality of MOS transistors connected in parallel between the first input node and the first output node, and the digital driving circuit drives the first voltage down converting partial circuit to change stepwise the number of MOS transistors to be activated among the plurality of MOS transistors according to the level of the internal power supply voltage.
The digital driving circuit sets the number of the MOS transistor to be activated to the number such that the operating current of the reference current value flows when the internal power supply voltage is at the level of the reference voltage; sets the number of the MOS transistor to be activated to the number such that the current generated by decreasing the current stepwise from the reference current value flows when the internal power supply voltage rises above the level of the reference voltage; and sets the number of the MOS transistor to be activated such that the current generated by increasing the current amount stepwise from the reference current value flows when the internal power supply voltage falls below the reference voltage. Then, the first voltage down converting partial circuit passes such operating current from the first input node to the first output node that the voltage on the first output node is maintained at the level of the internal power supply voltage based on the drive from the digital driving circuit by changing the number of MOS transistors to be activated. Hence, according to the present invention, regardless of the variation of the internal power supply voltage, the voltage on the first output node can be maintained at the level of the internal power supply voltage through the change in the channel width of the MOS transistor.
Preferably, the digital driving circuit of the first voltage down converting circuit includes a voltage divider circuit to divide the external power supply voltage into a plurality of voltages corresponding to the plurality of MOS transistors, and a digital signal generation circuit to generate a digital activation signal based on the plurality of voltages only during a period when the internal power supply voltage falls below a predetermined voltage, and the voltage divider circuit divides the external power supply voltage to generate the digital activation signal to change stepwise the number of MOS transistors to be activated according to the level of the external power supply voltage.
The voltage divider circuit divides the external power supply voltage into a plurality of voltages according to the level thereof. When the external power supply voltage varies from the level of the reference voltage, the external power supply voltage is divided according to the resulting level from variation. When the external power supply voltage rises, the levels of the divided voltages rise, too, whereas if the external power supply voltage falls, the levels of the divided voltages fall, too.
Then, the digital signal generation circuit generates a digital activation signal for activating the MOS transistor of necessary numbers for the first voltage down converting partial circuit to pass the reference current value when the external power supply voltage is at the level of reference voltage. In addition, the digital signal generation circuit generates a digital activation signal for decreasing stepwise the number of MOS transistors to be activated when the external power supply voltage is higher than the level of the reference voltage. Further, the digital signal generation circuit generates a digital activation signal for increasing stepwise the number of the MOS transistors to be activated when the external power supply voltage is lower than the level of the reference voltage.
Then, in the first voltage down converting partial circuit, the MOS transistors of such numbers are driven that the voltage on the first output node is maintained at the level of the internal power supply voltage based on the digital activation signal from the digital driving circuit. Therefore, according to the present invention, the voltage on the first output node can be maintained at the level of the internal power supply voltage regardless of the variation in the external power supply voltage.
Preferably, the digital driving circuit in the first voltage down converting circuit includes a voltage divider circuit to divide the internal power supply voltage into a plurality of voltages corresponding to the plurality of MOS transistors, and a digital signal generation circuit to generate a digital activation signal based on the plurality of voltages only during a period when the internal power supply voltage falls below a predetermined voltage, and the voltage divider circuit divides the internal power supply voltage to generate the digital activation signal changing stepwise the number of MOS transistors to be activated according to the level of the internal power supply voltage.
The voltage divider circuit divides the internal power supply voltage into a plurality of voltages according to the level thereof. When the internal power supply voltage varies from the level of the reference voltage, the internal power supply voltage is divided according to the resulting level from variation. When the internal power supply voltage rises, the levels of the divided voltages rise, too, whereas if the internal power supply voltage falls, the levels of the divided voltages fall, too.
Then, the digital signal generation circuit generates a digital activation signal for activating the MOS transistor of necessary numbers for the first voltage down converting partial circuit to pass the reference current value when the internal power supply voltage is at the level of reference voltage. In addition, the digital signal generation circuit generates a digital activation signal for decreasing stepwise the number of MOS transistors to be activated when the internal power supply voltage is higher than the level of the reference voltage. Further, the digital signal generation circuit generates a digital activation signal for increasing stepwise the number of the MOS transistors to be activated when the internal power supply voltage is lower than the level of the reference voltage.
Then, in the first voltage down converting partial circuit, the MOS transistors of such numbers are driven that the voltage on the first output node is maintained at the level of the internal power supply voltage based on the digital activation signal from the digital driving circuit. Therefore, according to the present invention, the voltage on the first output node can be maintained at the level of the internal power supply voltage regardless of the variation in the external power supply voltage.
Preferably, the voltage divider circuit included in the digital driving circuit of the first voltage down converting circuit is constituted of a plurality of resistance elements connected in series between the first input node and the ground terminal, and the digital signal generation circuit includes a plurality of nodes provided respectively between plurality of resistance elements to generate the plurality of voltages, a plurality of inverters provided corresponding to the plurality of nodes to convert voltages on the plurality of nodes to an output signal of a first logic or a second logic according to a level of the voltage, and a plurality of logic elements provided corresponding to the plurality of inverters to generate the digital activation signal based on a signal attaining the first logic only during a period when the internal power supply voltage falls below a predetermined voltage and an output signal from each of the plurality of inverters, and each of the plurality of logic elements generates a signal to activate the MOS transistor when the output signal is in the first logic.
To the plurality of resistance elements forming the voltage divider circuit, a current is supplied from the external power supply voltage or the internal power supply voltage. Then, the plurality of resistance elements divide the external power supply voltage or the internal power supply voltage into the plurality of fractions of voltage.
The voltage divider circuit supplies the plurality of fractions of voltage into a plurality of inverters via a plurality of nodes and the plurality of inverters convert the inputs to a signal of an H level or an L level according to the level of the input voltage. When the input voltage is lower than a threshold value, the inverter outputs an H level signal and when the input voltage is higher than the threshold value, the inverter outputs an L level signal. Each of the plurality of logical elements receives an output signal of an inverter and a signal attaining an H level only during a period when the internal power supply voltage is lower than a predetermined voltage. Further, each of the plurality of logical elements performs an NAND operation of two signals when the MOS transistor forming the first voltage down converting partial circuit is a P channel MOS transistor and performs an AND operation of two signals when the MOS transistor forming the first voltage down converting partial circuit is an N channel MOS transistor. Thus, the plurality of fractions of voltage generated by the voltage divider circuit can be converted into digital signals reflecting the variation thereof. In addition, the digital activation signal activating the MOS transistor can be output only during a period when the internal power supply voltage falls below a predetermined voltage.
Preferably, the voltage divider circuit included in the first voltage down converting circuit is activated only during a period when the internal power supply voltage falls below a predetermined voltage and the voltage divide circuit further includes an MOS transistor provided between the plurality of resistance elements and the ground terminal.
When the internal power supply voltage is not lower than a predetermined voltage, the MOS transistor is inactivated and the current which flows from the first output node through the plurality of resistance elements in the voltage divider circuit is blocked at the MOS transistor. Hence, generation of a through current can be prevented in the voltage divider circuit when the first voltage down converting circuit is not driven.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.